The present invention generally relates to printed circuit boards, and, more particularly, the present invention relates to printed circuit boards having plated vias or holes.
In general, any structure that allows a signal to propagate from one point to another is defined as a transmission line. As a signal propagates along a transmission line, both a voltage and current are present. The ratio of these two parameters is defined as the characteristic impedance of the line. The characteristic impedance is a property that is determined solely by the material and geometry of the transmission line. The characteristic impedance of the transmission line is proportional to the ratio of the inductance and capacitance of the line. In general impedance is dependent upon frequency, but for lines that are essentially lossless, such as connectors and high quality cables, it can be considered constant.
When a transmission line is used to connect two points, ideally the signal arriving at the receiver end will be the same as that which entered the line at the driver end. However, if the transmission line changes characteristic impedance at any point along the way, such as occurs when a connector is placed between two circuit boards, the behavior becomes more complicated. At the interface where such an impedance change occurs, partial reflections of the signal will be created. These reflected waves will travel back toward the source where they may be re-reflected a second time. At each interface where an impedance change occurs, a reflected signal will be created. The reflections caused by these impedance mismatches have the ability to alter the original signal transmission. They can be very problematic because they can cause logic circuits to switch inadvertently. Furthermore, as signal risetimes drop below 1 ns, connectors, chip sockets and even circuit board vias begin to create large enough reflections as to potentially cause significant signal transmission concerns. Consequently, as clock rates increase and signal risetimes become short, all portions of the interconnection path need to be well matched to the impedances of the circuit boards and components they interconnect in order to avoid creating signal integrity problems.
Vias are created in printed circuit boards by forming metallic pads on the top and bottom surfaces of the board and on inner signal layers, drilling through holes through the pads and plating a hollow barrel of metal between the pads. Vias allow connections to be made between the inner signal layers or planes and the outside surfaces of the board. Vias are also used to connect outside components (such as connectors, surface mount components or integrated circuit chips) with the internal signal layers in the board.
The impedance of a via can be determined from its inductance and capacitance. The capacitance is created by the stray electric field present between the via and the various power or ground layers in the circuit board. The inductance of the via is related to the magnetic field surrounding the portion of the via carrying the signal current. Typically the inductance of the via is quite small relative to its capacitance. As such, most vias exhibit a very low impedance and are a poor match to typical circuit board trace impedances of 50-75 Ohms.
The impedance mismatches associated with vias are particularly difficult to address. Whereas the geometry of connectors and chip sockets can, with care, be designed to match the impedance of the components they will connect, few avenues are available to match the impedance of vias to the elements they interconnect. Reducing the via""s capacitance or increasing the via""s inductance will raise the via""s impedance and create an improved match. This improvement will improve the capability to carry higher data rates from the circuit board through the via to the outside world. One may reduce the capacitance of the vias by reducing the length of the viasxe2x80x94for example, by counterboring the backside of the boards. Counterboring does not allow routing of signals to layers near the bottom of the printed circuit board. This limitation greatly reduces signal routing possibilities.
Other similar techniques for reducing the capacitance of the vias include reducing the diameter of the vias or increasing the clearance between the vias and the internal circuit board layers. In each case the idea is to reduce the electrostatic coupling between the via barrel and the conductor planes in the printed circuit board. Both of these techniques have drawbacks as well. Smaller diameter vias are more difficult to plate, particularly in thick printed circuit boards. Increasing the clearance between the vias and the internal circuit board layers can render large portions of the layers useless in regions where multiple vias are placed close together such as where a connector mounts to the board.
According to one aspect of the present invention, a method for improving the impedance match of a via having a conductive plating lining the inner wall thereof (also referred to herein as a xe2x80x9cmetal barrel or cylinderxe2x80x9d) includes a step of increasing the inductance of the via and, thus, its impedance as well. According to another aspect of the present invention, the step of increasing the inductance of the via includes a step of inserting a small inductive coil in the via. According to still another aspect of the present invention, the step of increasing the inductance of the via having a metal barrel includes a step of tapping a screw thread into the metal barrel to transform it into a short helical coil or strip. The inductance produced from this approach can be tightly controlled based on the pitch, width, and number of turns of the screw thread implemented in the via. The geometry of the helical coil can be tuned to obtain an inductance that allows the impedance of the via to be matched to the impedance of the circuit board.
According to a further aspect of the present invention, a method of increasing the inductance of the via without altering its geometry includes a step of plating the via with a paramagnetic or ferromagnetic material (such as nickel) to form a conductive barrel, instead of plating the via with the usual tin-lead over copper compound.
According to still another aspect of the present invention, a method for improving the impedance match of a via includes a step of reducing the capacitance of the via and, thereby increasing its impedance. According to yet another aspect of the present invention, the step of reducing the capacitance of the via having a metal barrel includes a step of cutting material from the metal barrel to leave at least one conductive strip or band extending axially along the wall of the via. According to still another aspect of the present invention, the step of reducing the capacitance of the via having a metal barrel includes a step of cutting material from the metal barrel to leave a plurality of conductive strips or bands extending axially along the wall of the via with axially extending, non-conductive spaces between the conductive strips.
Additional features of the present invention will become apparent to those skilled in the art upon a consideration of the following detailed description of the preferred embodiments exemplifying the best mode of carrying out the invention as presently perceived.